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ISE Design Suite 13.1
New Blocks
Complex Multiply 5.0
This block is based on the Xilinx? LogiCORE? IP Complex Multiplier that implements
AXI4-Stream compliant, high performance, optimized complex multipliers based on user-
specified options.
DSP48 Macro 2.1
The Xilinx LogiCORE? DSP48 Macro provides an easy-to-use interface that abstracts the
XtremeDSP? slice and simplifies its dynamic operation by enabling the specification of
multiple operations via a set of user-defined arithmetic expressions. New in this version of
the core is the ability to control resets and clock enables of the registers within the
XtremeDSP Slice.
DSP48E1
The Xilinx DSP48E1 block is an efficient building block for DSP applications that use Xilinx
Virtex?-6 devices. The DSP48E1 block provides access to the pre-added and control of the
registers within the silicon.
FIR Compiler 6.2
This block is based on the Xilinx? LogiCORE? IP FIR Compiler v6.2 that implements
AXI4-Stream compliant, high performance, optimized complex multipliers based on user-
specified options.
VDMA Interface 3.0 (Beta)
This block is based on the AXI Video Direct Memory Access (AXI VDMA) core which is a
soft Xilinx IP core providing high-bandwidth direct memory access between external DDR
memory and the AXI4-Stream interface. Initialization, status, and management registers
are accessed through an AXI4-Lite slave interface which can be configured using an
MCode block. A MATLAB utility function is provided to generate the necessary logic to
easily connect your System Generator design to external DDR memory.
Previous Versions of System Generator for DSP Release Notes
Previous versions of System Generator for DSP release notes are located in Chapter 3 of the
System Generator for DSP Getting Started Guide (v 12.4) . This getting started guide is
located online at the following URL:
http://www.xilinx.com/support/documentation/dt_sysgendsp_sysgen12-4.htm
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
www.xilinx.com
27
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